1. Field of the Invention
The present invention relates to a test apparatus and a test method. More particularly, the present invention relates to a test apparatus and a test method for a device under test such as a semiconductor device.
2. Related Art
A test apparatus for a semiconductor device or the like, for example, supplies a test signal with a predetermined level to the semiconductor device. The test apparatus includes a rising edge generator for generating a rising edge timing and a falling edge generator for generating a falling edge timing, and generates a test signal with a waveform according to the edge timings generated from these edge generators as disclosed, for example, in Japanese Patent Application Publication No. 1996-146099. Each edge generator generates an edge timing based on a delay time from a start time of a reference clock period that is a period for a reference clock and edge information showing an edge type.
An edge generator has a delay device with a variable delay time, and controls this delay device to generate an edge at a predetermined timing. The edge generator sets a delay amount of the delay device every reference clock period. For this reason, in order to generate a test signal including two rising edges and two falling edges during the reference clock period, a conventional test apparatus has included two edge generators for a rising edge and two edge generators for a falling edge to generate a prior edge and a subsequent edge from the edge generators different from each other.
In addition, since prior art documents are not recognized now, the description related to the prior art documents is omitted.
Meanwhile, the test apparatus converts a test pattern expressed in a unit of a test period set by a user into edge information every reference clock period, and generates the above test signal based on edge information after the conversion. Therefore, when a phase of the reference clock period for the test period deviates due to a fluctuation of the test period, it is necessary that the test apparatus makes the same edge generator generate two rising edges or two falling edges during the reference clock period depending on a generation timing of an edge even though the test apparatus has two rising edge generators and two falling edge generators. In this case, the test apparatus violates restriction (proximity restriction) that only one edge is generated from one edge generator during the reference clock period.